Non-volatile memory cells and array are well known in the art. Typically, in operation a non-volatile memory cell/array requires that low voltage and high voltage be supplied to the cell/array, for certain operations. Further, it is well known that memory cells are arranged in an array of a plurality of rows and columns, with cells in the same column being connected to the same bit line to one or more sense amplifiers. Cells in the same row share certain common lines such as word line and/or erase lines. As processing technology permits further scaling more and more cells are connected in the same row, creating sectors with larger number of cells connected to the same row line. Thus, as scaling increases, sector size also increases. This poses a problem in that as more cells are connected to a common row line, the voltage drop across that row line from the point where the first memory cell is connected to the row line to the last memory cell connected to that same row line would increase. This creates potential error problems.
Referring to FIG. 1 there is shown a schematic cross-sectional view of a non-volatile memory cell 10 of the prior art which can be used to form a non-volatile memory array of the present invention, although as will be seen, the present invention is not limited to the memory cell of the type shown in FIG. 1. The memory cell 10 comprises a substrate 12 of a semiconductor material of a first conductivity type, such as P type. A first region 14 (drain region or BL) of a second conductivity type, such as N, is along the surface of the substrate 12. Spaced apart from the first region 14 is a second region 16 (source region or SL) also of the second conductivity type. Between the first region 14 and the second region 16 is a channel region 18. As is well known, charges travel the channel region 18 from one region 14 or 16 to the other region 16 or 14. A bit line typically connects to the first region 14. Cells in the same column in the array have the same bit line connected in common.
A word gate or WL 20 is insulated from the channel region 18 and is over a portion of the channel region 18. A floating gate 22 is adjacent to the word gate 20 and is insulated therefrom and is over another portion of the channel region 18. A control gate (also known as coupling gate) or CG 24 is over the floating gate and is capacitively coupled thereto. Finally, an erase gate or EG 26 is adjacent to the floating gate 22 to another side of the floating gate 22 and is insulated therefrom. The erase gate 26 is also over the source region 16 and is insulated therefrom.
In certain operations of the memory cell 10, low voltages are applied. For example, during a read operation, low voltages are applied to the word gate 20, the coupling gate 24, and the source region 16. In other operations, high voltages are applied. For example, during erase operation, high voltage is applied to the erase gate 26. Yet in other operations, both low voltage and high voltages are applied simultaneously. Thus, during programming, low voltage is applied to the word gate 20, while high voltage is applied to the control gate 24 and to the source region 16.
Referring to FIG. 1A there is shown a non-volatile memory array and pitch 30 of the prior art as an example. An array 31 consists of 4096 (4K) columns and 2048 (2K) rows of memory cells. Each memory cell has five terminals (BL, WL, CG, EG, SL coupled to (bitline) drain region 14, word gate 20, control gate 24, erase gate 26, and source region 16 respectively) as described above. The array 31 is organized as a plurality of sectors. Each sector, for example, consists of 8 rows and 4096 columns, making up a total of 4 KB (4096 bytes). All memory cells in a 4 KB sector are erased at same time and may be programmed at different times. This small sector size of 4 KB is needed for typical microcontroller system application for handling small size of data (such as system configuration data, date, time, tags, manufacturing ID, product ID, security code, etc). Within each sector there are 8 poly lines of word-lines WL<0:7>, 4 poly lines of erase gate EGs (since each erase gate EG is shared between two neighboring top and bottom cells), 8 poly lines of control gates CGs, 4 diffusion lines of source-lines SLs (since each diffusion source line SL is shared between two neighboring cells). These poly lines or diffusion lines may be segmented at certain intervals to make room for metal lines to strap to those poly or diffusion segments so as to reduce time delay or voltage drop across the array 31. Since all cells in a sector are erased together, all 4 poly erase gates are connected together to form electrically one erase gate per 4 KB sector (that consists of 8 rows and 4K bitlines of memory cells). Also typically all 8 poly control gates are connected together to form electrically one control gate or two control gates per sector. Also all 4 diffusion source lines are connected together to form electrically one source line per sector. Alternative sector size organization is possible such as 8 KB sector size which might consists of 16 rows and 4K bitlines or of 8 rows and 8K bitlines, or such as 16 KB sector size which might consists of 16 rows and 8K bitlines or of 32 rows and 4K bitlines. Alternative sector size such as 32 KB or greater is possible.
With each array 31 there is an associated a first decoder (XDEC) 32 and a second decoder (WSHDRV) 34. A memory chip may include a plurality of arrays 31 and decoders 32 and 34. Not shown is y-decoder (column decoder) which provides the column (bitline BL) selection. The first decoder 32 provides selection for wordline WLs for 2048 rows of memory cells. The second decoder 34 provides selection for the control gates CGs, erase gate EGs, and source-line SLs for 2048 rows of memory cells. The first decoder 32 includes a plurality of decoder 42 (described below). Each decoder 42 is used for an array sector (8 rows). The second decoder 34 includes a plurality of decoders 44 (described below). Each decoder 44 is used for an array sector (8 rows).
Referring to FIG. 1B there is shown another prior art non-volatile memory array 41 with decoders 42 and 44 as an example of 4 KB sector array and its associated decoders. Each sector is shown with 8 (strapping) metal-line wordline WL<0:7> (coupled to the word gate 20 of memory cells), one (strapping) metal-line control gate CG<0> (coupled to control gate 24 of memory cells), one (strapping) metal-line erase gate EG<0> (coupled to erase gate 26 of memory cells), and one (strapping) metal-line source line SL<0> (coupled to source region 16 of memory cells) and 4K bitlines (columns (BL0 to BL4096) coupled to bitline (drain) region 14 of memory cells). NMOS transistor 46A and 46B are used to pull the source line SL<0> to virtual ground, e.g. around zero volt, in read condition. Operating condition for such array is shown in the following Table 1.
TABLE 1Operating Array Conditions (in volts)EraseProgramReadSelected SectorSelected WL (1/8 WLs selected)0VwlprogVwlrdUnselected WL (7/8 WLs unselected)000EG0Veger0/Vegprog0/VegrdCG00VcgprogVcgrdSL00Vslprog0Unselected SectorsEGs000/VegrdCGs0/Vcgrd0/Vcgrd0/VcgrdSLs0VUNSELprog0Selected BL0IprogVrdblUnselected BLs0VINH0Where exemplary voltages and currents are as follows:Vwlrd1.2-2.5vWord line read biasVcgrd1.2-2.5vControl gate read biasVegrd1.2-2.5vErase gate read biasVblrd0.3-1.6vBitline read biasVeger8.0-12.0vErase gate erase voltageVslprog3.5-5.0vSource line program voltageVunslprog0.0-2.0vUnselected source line program voltageVwlprog0.8-1.8vWord line program voltageVcgprog8.0-12.0vControl gate program voltageVegprog3.5-5.0vErase gate program voltageIprog0.1-10uAProgram current biasVINH1.2-2.5vInhibit voltage on unselected bitline
In the embodiment shown in FIGS. 1A and 1B and in the figures set forth herein, bitlines BL0-BLN are in metal1, wordlines WL0-N, CGs, EGs, are in (strapping) metal2, and source lines SLs are in (strapping) metal3. Metal material can be Tungsten, Aluminum, Copper or any other conductive material. Alternatively different number, such as 4-7 metal layers, or different arrangements of strapping metal layers, such as changing vertical and horizontal directions of the strapping metal layers, can be used. Via layers are used to strap metal layers to poly or diffusion layer of memory cells and are not shown (called array metal strapping). Array metal strapping frequency (how frequent, i.e. strapping per how many bitlines, metal layer making contact to poly or diffusion layer of memory cells) is typically more frequent for source line and wordline and less frequent for control gate and erase gate.
Referring to FIG. 1C there is shown a schematic circuit diagram of the non-volatile memory array 41 shown in FIG. 1B. As shown symbolically is a schematic of two memory arrays 41 (41A and 41B) with each array 41 consisting of 8 rows and 4K bitlines making up a 4 KB array sector. The 4 KB sector thus consists of 8 WLs, 1 CG, 1 SL, and 1 EG. Top (horizontal) metal strapping layers are not shown for clarification purpose. Vertical metal strap line 43 is shown per sector for connecting 4 poly erase gates into one EG, 4 diffusion source lines into one SL, 8 poly control gates into one CG (not shown for WL). Strap for EG, SL, CG is shown to be next to each other at one physical place. Strapping frequency (how often the top metal connect through via to poly or diffusion layer of memory cells) is not shown. Typical strapping frequency for SL or WL is per 8, 16, 32 memory cells and for EG or CG is less frequent than that of SL or WL.
The problem is that as scaling increases, the memory cell area is reduced at a greater ratio than the pitch circuitry (meaning the decoders 32/42 and 34/44) causing the decoder area overheads to be significant portion of the die-size. One reason the decoder area is not reduced in the same ratio as the scaling ratio is that the operating voltage condition for non-volatile erase and program operation remains very high. Hence an innovation is needed to reduce the pitch decoder overhead, especially to maintain the same small sector size without degrading the electrical performance such as disturb in programming. Another challenge is that as the size of various features is reduced, the electrical parasitic such as source line diffusion resistance increases. This causes greater voltage drops, in low voltage as well as in high voltage condition, from one end of a row line to another end, for voltages that are applied to that row line.
It is therefore, desirable to decrease the variation in the voltage drop in a row line.